1. Field of the Invention
The present invention relates to a circuit module and, in particular, to an error detection in a circuit module comprising a module board and a plurality of circuit chips arranged on the module board.
2. Description of the Related Art
A conventional structure of computer main memory systems includes a memory controller, a main memory bus and memory chips, DRAM chips for example, that are arranged on memory modules, DIMMs (DIMM=Duals In-Line Memory Module) for example. The main memory bus connects the memory modules to the memory controller. In general, the main memory bus comprises a data bus, a command/address bus, and lines carrying clock signals and check signals.
Conventionally, error detection and correction on the main memory bus is done on the data bus only, by including additional bits or even chips and by using special algorithms for processing data received via the data bus.
Some prior art computer main memory systems comprise additional error detection means to detect errors on the command/address bus. In such systems, the memory controller generates a check signal which is driven to the memory modules. Each memory module comprises an error detection unit that detects an error on the command/address bus by making use of the check signal. In case of a detected error, the error detection unit generates an error signal that is driven back to the memory controller.
FIG. 1 shows a schematic view of such a prior art memory module. The memory module is in the form of a registered DIMM. The memory module comprises a module board 100, a plurality of memory chips (DRAMs) 102, a buffer or register 104 and a connector portion 106. The connector portion 106 is connected to the buffer or register 104 via a module main bus 108. At the output of the buffer or register 104, the module main bus 108 branches into sub-busses 110 each of which being connected to one of the memory chips 102.
The connector portion 106 comprises a plurality of terminals 120 to 124 to receive or drive a plurality of signals from or to a memory bus on a motherboard (not shown) to which the memory module is connected. A clock signal CLK is applied at terminal 120, address signals A0 and Al are applied at terminals 121 and 122, a check signal Parity IN is applied at terminal 123 and an error signal Parity OUT is applied at terminal 124. In FIG. 1 only those components necessary to explain the functionality of interest, i.e. the components associated to the command/address bus are shown. Moreover, for simplicity, only two address bits A0 and A1 of the command/address bus are shown, while usual command/address busses comprise 24 to 27 bits.
The buffer or register 104 comprises buffer or register elements, drivers 130, 131 and 132 and an error detection circuit, comprising XOR-gates 141 and 142.
The drivers 130 and 131 are operable to drive the address lines and are controlled by the clock signal CLK.
First and second inputs of the first XOR-gate 141 are connected to the terminals 122 and 123, respectively. Thus, the memory bus signals A1 and Parity IN provide the input signals for the first XOR-gate 141. The output 145 of the first XOR-gate 141 is connected to a first input of the second XOR-gate 142 which is also connected to the terminal 121. The terminal 121 provides the A0 bit, which is the next less significant bit of the memory bus bits. The output 146 of the second XOR-gate 142 is connected to the driver 132 which samples the output 146 with the signal CLK. The output of the driver 132 is connected to the terminal 125 which applies the error signal Parity OUT to the memory bus.
The error detection circuit provides error detection by way of parity checking. The check signal Parity IN provides a parity bit for the memory bus signal bits A0 and A1 that is generated and provided by a memory controller (not shown). The value of the parity bit depends on the number of “1” bits on the memory bus signals A0 and A1, at a time. If there is an odd number of “1” bits, the corresponding parity bit has a high value, otherwise if there is an even number of “1” bits, the parity bit has a low value. The Parity Checking is done by way of XOR-gates. There are as many XOR-gates as there are bits on the memory command/address bus. The output of each XOR-gate and the next less significant command/address bus bit, referred to the command/address bus bit taken as input for the current XOR-gate, are taken as input for the next XOR-gate. The output bit of the last XOR-gate is an error bit and is driven back to the memory controller.
The Signal Parity OUT has a low value as long as there is no error detected on the module main bus 108 by the error detection circuit. In case of a single bit error the Signal Parity OUT will turn to an high value. A memory controller that checks the Signal Parity OUT can therefore detect single bit errors on the memory bus. Multiple bit errors cannot be detected for sure.
The error detection method as described in FIG. 1 is restricted to registered (buffered) memory modules and has the disadvantage that errors that occur on one of the sub-busses 110 are not detected.
The complexity of non-protected sub-buses on a memory module of a kind as shown in FIG. 1 is illustrated in FIG. 2. FIG. 2 shows a schematic view of a computer main memory system comprising a memory controller 200 and a plurality of memory modules 202 in the form of registered DIMMs. The memory controller 200 is connected to a main memory bus 204, which branches into a plurality of memory busses 206 each of which is connected to one of the memory modules 202. The main memory bus 204 is terminated by a termination resistor 208.
Each memory module 202 comprises a plurality of memory chips 210 in the form of DRAM chips. To be more specific, in the embodiment shown in FIG. 2 four memory modules 202 are shown and nine memory chips 210 are arranged on each memory module 202. Each memory module 202 comprises a buffer or register 212 that comprises error detection circuit elements as described in FIG. 1. (The error detection circuit elements are not shown in particular in FIG. 2.) On each memory module 202 a module main bus 214 connects the respective memory bus 206 to the buffer or register 212. At the output of the buffer or register 212 the module main bus 214 branches into a plurality of sub-busses 216 each of which is connected to one of the memory chips 210. This high number of sub-busses 216 is not protected by the error detection circuit elements that are embedded in the registers 210. Thus, as outlined above, errors that occur on command/address lines of the sub-busses 216 cannot be detected according to this prior art approach.